Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers
نویسندگان
چکیده
منابع مشابه
Parallel reduced area multipliers
As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that result...
متن کاملEfficient modulo 2n+1 tree multipliers for diminished-1 operands
In this work we propose a new method for designing modulo 2"+I multipliers for diminished-I operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.
متن کاملEfficient modulo 2+1 Tree Multipliers for Diminished-1 Operands
In this work we propose a new method for designing modulo 2+1 multipliers for diminished-1 operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.
متن کاملTwo Operands of Multipliers in Side-Channel Attack
The single-shot collision attack on RSA proposed by Hanley et al. is studied focusing on the difference between two operands of multipliers. There are two consequences. Firstly, designing order of operands can be a cost-effective countermeasure. We show a concrete example in which operand order determines success and failure of the attack. Secondly, countermeasures can be ineffective if the asy...
متن کاملAutomatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers
This paper presents a system for the automatic generation of Galois-field (GF) arithmetic circuits, named the GF Arithmetic Module Generator (GF-AMG). The proposed system employs a graph-based circuit description called the GF Arithmetic Circuit Graph (GF-ACG). First, we present an extension of the GF-ACG to handle GF(pm) (p ≥ 3) arithmetic circuits, which can be efficiently implemented by mult...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IPSJ Transactions on System LSI Design Methodology
سال: 2011
ISSN: 1882-6687
DOI: 10.2197/ipsjtsldm.4.131